Asynchronous Network-on-Chip Architecture for Neuromorphic Processor
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摘要:
类脑处理器较深度学习处理器具有能效优势.类脑处理器的片上互连一般采用具有可扩展性高、吞吐量高和通用性高等特点的片上网络.为了解决采用同步片上网络面临的全局时钟树时序难以收敛的问题以及采用异步片上网络面临的链路延迟匹配、缺乏电子设计自动化工具实现和验证的问题，提出了一种异步片上网络架构——NosralC，用于构建全局异步局部同步（global asynchronous local synchronous， GALS）的多核类脑处理器. NosralC采用异步链路和同步路由器实现.实验表明，NosralC较同步基线，在4个类脑应用数据集下展现出37.5%~38.9%的功耗降低、5.5%~8.0%的平均延迟降低和36.7%~47.6%的能效提升，同时增加不多于6%的额外资源以及带来较小的性能开销（吞吐量降低0.8%~2.4%）. NosralC在现场可编程门阵列（FPGA）上得到了验证，证明了该架构的可实现性.
Abstract:Neuromorphic processors show extremely high energy efficiency advantages over traditional deep learning processors. The network-on-chip with high scalability, high throughput, and high versatility features is generally adopted as the on-chip communication and connection implementation of neuromorphic processors. In order to solve the problems of making the synchronous network-on-chip that adopts the global clock tree to achieve timing closure, matching link delay in the asynchronous network-on-chip, and lacking electronic design automation tools in implementation and verification of asynchronous network-on-chip, we propose a low-power asynchronous network-on-chip architecture, NosralC, to build a global-asynchronous-local-synchronous multi-core neuromorphic processor. NosralC is implemented with asynchronous links and synchronous routers. The small amount of asynchronous design makes NosralC similar to the synchronous design and friendly to implementation and validation of asynchronous design using existing electronic design automation tools. Experiments show that compared with a synchronous counterpart baseline with the same function, NosralC achieves 37.5%−38.9% reduction in power consumption, 5.5%−8.0% reduction in average latency, and 36.9%−47.6% improvement in energy efficiency in executing the FSDD, DVS128 Gesture, NTI-DIGITS, and NMNIST neuromorphic application datasets while increasing less than 6% additional resource overhead and a small amount of performance overhead (0.8%−2.4% throughput decrease). NosralC is verified on the field programmable gate array (FPGA) platform and its implementability is proved.
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图 7 类脑处理器片上互连通信NoC架构框图
Figure 7. Block diagram of NoC architecture for on-chip interconnection and communication of neuromorphic processor
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图 10 输入模块设计和X-Y路由算法示意图
Figure 10. Design of input module and schematic of X-Y routing algorithm
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图 11 输出模块设计和轮询仲裁机制示意图
Figure 11. Design of output module and schematic of round robin arbitrating mechanism
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图 12 异步链路的数据通路和控制电路框图
Figure 12. Block diagram of data channel and control circuit of asynchronous link
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图 13 同步域与异步域数据转换电路写通道
Figure 13. Writing channel of data conversion circuit between synchronous domain and asynchronous domain
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图 14 同步域与异步域数据转换电路读通道
Figure 14. Reading channel of data conversion circuit between synchronous domain and asynchronous domain
表 1 液体状态机SNN配置
Table 1 Configuration of Liquid State Machine SNN
参数 数量/类型 输入层神经元数量 256 液体层神经元数量 1000 液体层中的激活型神经元数量 800 液体层中的抑制型神经元数量 200 输出层 1000×10全连接层 激活型→激活型神经元连接概率 0.4 激活型→抑制型神经元连接概率 0.4 抑制型→激活型神经元连接概率 0.5 抑制型→抑制型神经元连接概率 0 
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表 2 同步同等设计基线与NosralC的功耗对比
Table 2 Power Comparison Between Synchronous Counter part Baseline and NosralC
测试数据集 功耗类型 功耗/mW 减幅/% 同步同等设计 NosralC FSDD 静态 165.0 96.7 41.4 动态 21.4 19.8 7.5 总功耗 186.4 116.5 37.5 NTI-DIGITS 静态 165.0 96.7 41.4 动态 19.7 16.3 17.4 总功耗 187.4 113.0 38.8 DVS128
Gesture静态 165.0 96.6 41.5 动态 18.8 17.9 4.5 总功耗 183.8 114.5 37.7 NMNIST 静态 166.0 96.9 41.6 动态 24.8 19.7 20.6 总功耗 190.8 116.6 38.9 平均 静态 164.0 96.1 41.4 动态 20.8 18.2 12.4 总功耗 184.8 114.3 38.1
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表 3 同步同等设计基线与NosralC的平均延迟对比
Table 3 Average Delay Between Synchronous Counterpart Baseline and NosralC
测试数据集 平均延迟/周期 减幅/% 同步同等设计 NosralC FSDD 1098 1010 8.0 NTI-DIGITS 1035 952 8.0 DVS128 Gesture 1097 1036 5.5 NMNIST 1062 996 6.2 平均 1072.9 998.7 6.9
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表 4 同步同等设计基线与NosralC的吞吐量对比
Table 4 Throughput Comparison Between Synchronous Counterpart Baseline and NosralC
测试数据集 吞吐量/(报文/周期) 减幅/% 同步同等设计 NosralC FSDD 6.8 6.7 1.9 NTI-DIGITS 6.5 6.4 2.4 DVS128 Gesture 6.9 6.8 1.3 NMNIST 6.7 6.6 0.8 平均 6.7 6.6 1.6
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表 5 同步同等设计基线与NosralC的能效对比
Table 5 Energy Efficiency Comparison Between Synchronous Counterpart Baseline and NosralC
测试数据集 能效/(Mop/W) 增幅/% 同步同等设计 NosralC FSDD 500.1 683.4 36.7 NTI-DIGITS 493.7 714.3 44.7 DVS128 Gesture 534.4 734.7 37.5 NMNIST 461.2 680.8 47.6 平均 497.4 703.3 41.4
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表 6 同步基线与NosralC的资源利用量对比
Table 6 Resource Utilization Comparison Between Synchronous Counterpart Baseline and NosralC
FPGA资源 资源利用量 增幅/% 同步同等设计 NosralC LUT 563697 595769 5.7 FF 1332625 1367228 2.6 BUFG 1 1 0 平均 4.2
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表 7 NosralC与先进相关工作的比较
Table 7 Comparison of NosralC and the State of the Art Work
配置 TrueNorth Loihi NosralC 工艺 65nm ASIC 14nm ASIC FPGA 架构 2维Mesh 2维CMesh 2维Mesh 路由器 异步 异步 同步 链路 异步 异步 异步 节点数 4096 131 256 等效频率/MHz 0.001 153.8~243.9 20 平均延迟/ns 113~465 36440
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