As the CMOS technology enters the deep submicron design era, the richness of computational resources brings a lot of problems, such as complex clock distribution, great clock skew and high power dissipation. Asynchronous circuit style is an efficient approach to solve the problems, and it is becoming significantly attractive to designers. The asynchronous circuit design flow based on macrocells can convert a synchronous circuit to an asynchronous counterpart efficiently using current EDA tools and industrial libraries for the synchronous circuit design. In this paper, a fully-automated asynchronous circuit design flow based on macrocells is presented, and it is also compared with the fully-automated desynchronization flow. The fully-automated desynchronization flow generates asynchronous circuits from the gate-level netlist, while our flow works from the register transfer level specification. Then, the proposed flow is used to implement a simple DLX RISC microprocessor in UMC 018μm industrial library. The experiment shows that the fully-automated flow can accelerate the asynchronous circuit design and the logic delay of datapath in the macrocell based asynchronous circuit can be significantly optimized. Furthermore, the newly proposed flow can achieve an average of 6% speedups, when compared with the desynchronized DLX microprocessor for a subset of the Mibench benchmark suite.