With the rapid development pace of the SAR (synthetic aperture RADAR, SAR) missions, the demands for high data bandwidth of the satellite downlink are required. Reducing the data volume is the necessary task for the SAR missions. On-board SAR image processing has been one of the methods for effective reduction in data volume, since the SAR image data can be compressed much more easily than the SAR raw data. In recent years, FPGA-based real-time imaging for spaceborne SAR is an active research field. The goal of this research work is to design an FPGA-based system which can implement the real-time spaceborne SAR image processing. The parameters of spaceborne SAR are studied. Then a novel high-performance scalable architecture is proposed, which maps the CS (chirp scaling, CS) algorithm to the hardware system, through the analysis of the performance requirements and algorithm specifications. The prototype system implementation and functional verification are also presented. Experiment results show that with one signal processing unit that works at 50MHz, the system can process 512MB SAR raw data within about 11 seconds. The system has attractive merits on high performance and low mass, and is an excellent candidate for the real-time on-board SAR image processing system.