Efficiency and flexibility are crucial features of processors in embedded systems. The embedded processors need to be efficient in order to achieve real-time requirements with low power consumption for specific algorithms. And the flexibility allows design modifications in order to respond to different applications. In this paper, the configuration stream driven computing architecture (CSDCA) is proposed, which is both flexible and application specific hardware solution for implementation of embedded processors. Different from the traditional very long instruction word (VLIW) architecture or the transport triggered architecture (TTA), in the CSDCA, not only the responsibility of controlling the data transports is moved from the hardware to the compiler, but also the interconnect network between function units is visible to the compiler. So the routing can be performed by the compiler and the architecture can support the efficiency but complex interconnections to achieve low area overhead with low power dissipation. Directed by the CSDCA, an efficient design method for hardware implementation of application specific instruction-set (ASIP) processors is presented, which supports the reconfigurable segmented-bus networks. Experiment results with several practical applications show that the segmented-bus network can save 53% in power consumption and 38.7% in bus numbers, while maintaining the same speed compared with the simple-bus network.