Logarithmic converter is one of the most important components of logarithmic multipliers, which trades the computing precision for speed. It can be used in real-time applications, such as digital signal processing, which can tolerate loss in precision to a certain extent. In addition, hardware implementation of algorithms is another most important way to accelerate the execution of algorithms. In this paper an improved 32-bit binary logarithmic converter implemented in FPGA is presented. It is mainly composed of leading one detector, shifting logic and error correction circuit. Fast 4, 16, and 32-bit leading-one detector circuits are designed to obtain the leading-one position of an input binary word in parallel, which reduces the area and power-consumption estate while keeping the low delay. In addition, an improved 6-region algorithm is developed to reduce the maximum percent errors from current 30 percent to 20 percent, which greatly decreases the average error of the first region. The error correction circuit is implemented in double pipelined cycles with a bit more components to enlarge the throughput of the system; it maintains the regularity to reduce the complexity, area and power consumption of the system, while improving the precision of the computing. The design makes it possible to accelerate the processing of time-critical applications while keeping high precision.