To improve the performance of the entire computing system, not only the performance of CPU needs to be boosted, but also high performance chipsets are needed. Chipsets are responsible for data delivery between CPU and other devices, commonly with memory controllers embedded as crucial components, and this significance is highlighted as the memory access latency has become one of the most significant bottlenecks in nowadays computer systems. Discussed in this paper are the methods of designing and implementing a northbridge targeting at high performance. The architecture of NB2005—a northbridge for Godson-2 processor—and the optimization techniques applied on each module are described in detail. A novel dynamic page management strategy in DDR controller is proposed, which exploits the spatial locality characteristics of programs to reduce memory access latency. A new steam buffer mechanism is described, which at runtime jointly considers the memory access behavior and the status of memory controller. Also presented is a new buffer-swap mechanism implemented in PCI channel to improve the throughput of PCI bus. Experiments show that the Godson-2 system augmented with NB2005 outperforms that with Marvell GT64240 in all aspects tested. Specifically, NB2005 achieves above 40% memory bandwidth enhancement, yields speedups of 12.2%and 2.5% in SPEC INT2000 and SPEC FP2000 respectively and also improves the disk I/O performance by more than 30%.