Abstract: Hierarchical chip multicore processors (HCMPs) can well support the memory reference and on-chip communications locality through supernodes, each of which consists of several tightly coupled processing cores, and thus efficiently reduce the data communications latency. This paper revisits the previous costperformance Amdahl model of the multicore processors, and make some extentions to account for the non uniform data communications latency of the HCMP architectures. Through those extentions, this paper investigates the relationship between the performance speedup and the size of the supernodes, which means the number of cores in a supernode in hierarchical chip multicore processors, and some important design rules are maintained. Simulation results reveal that to maintain a better Amdahl speedup, the HCMP architecture designers should carefully deal with the size of the supernode and the number of supernodes in an HCMP. Given the overall number of processing cores in an HCMP, the configuration of the supernode that makes the HCMP the optimal performance is with the intermediate number of middle-sized supernodes, and the optimal size of the supernode also varies with the overall cores in the HCMP. During the design of a specific hierarchical chip multicore processor, the proposed performance model can be utilized to help the designers make a better decision.