Differential power analysis (DPA) attack is one of the most effective side channel attack technologies against the security chip. The success of DPA attack depends on two aspects: one is the correlation between power consumption and data, and the other is the synchronization of target function signals. Countermeasures based on power balanced logic styles aim to eliminate the power dependence. However, these methods introduce large performance, power, and area cost. Another effective way to counteract DPA attack is making the target function signals asynchronous. As the output signals of registers are always chosen as target function, the asynchronism can be achieved by randomizing the register switching time. The resistibility of register switching time randomization against DPA attack is analyzed theoretically at first. Then a novel countermeasure based on this idea is presented. The switching time of critical registers are randomized by the phase difference of different clock domains. The computing method of timing constraints to data and control signals transferred between the different clock domains is introduced. And the effect of clock frequencies on the randomization is analyzed. This countermeasure is implemented in an AES coprocessor, and the simulation experiment proves the correctness of the theoretical analysis. The simulation results show that this technology can improve the preventing ability of the cryptographic circuit under the special working clock frequency.