Scan-based pseudo-random BIST is currently one of the most popular structured design-for-testability (DFT) methodologies in very large scale integrated circuit test. However, excessive power dissipation and prohibitively long test time are two serious issues in this testing approach. Recently, various techniques have been proposed to address one of these issues. But few of them can deal with the two issues simultaneously. In this paper, a new scan-based BIST scheme, namely BIST scheme based on capture in turn of sub-scan chains (BCIT), is proposed. In this scheme, each scan chain is divided into N(N>1) sub-chains. During test, using scan chain disabling technique, all sub-chains in a scan chain are active in turn in both scan shift and capture cycles, i.e. only one sub-chain is active at a time. Thus, the switching activities in the scan cells can be limited to a low level. To detect random pattern resistant faults, an algorithm of LFSR seed generation, which is compatible with the proposed test scheme, is presented as well. Experimental results on ISCAS’89 benchmark circuits show that compared with the conventional BIST scheme, the proposed strategy can achieve not only about (N-1)/N reductions of average and peak power, but also significant reduction of test application time and seed storage for LFSR reseeding.