ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2018, Vol. 55 ›› Issue (5): 1065-1077.doi: 10.7544/issn1000-1239.2018.20170254

• 软件技术 • 上一篇    下一篇



  1. (西安交通大学计算机科学与技术系 西安 710049) (
  • 出版日期: 2018-05-01
  • 基金资助: 

FTL Address Mapping Method Based on Mapping Entry Inter-Reference Recency

Zhou Quanbiao, Zhang Xingjun, Liang Ningjing, Huo Wenjie,Dong Xiaoshe   

  1. (Department of Computer Science and Technology, Xi’an Jiaotong University, Xi’an 710049)
  • Online: 2018-05-01

摘要: 经典的闪存转换层(flash translation layer, FTL)地址映射方法DFTL(demand-based FTL)将全局映射信息放在闪存中,仅缓存最近最常使用的映射信息,解决了页级映射策略中映射信息较大和缓存容量有限的矛盾.但是,DFTL没有充分利用负载的空间局部性特点提高缓存命中率;在缓存失效时频繁的脏映射项换出也会导致大量的映射页写操作;此外,它未能优化垃圾回收过程中有效页迁移导致的写放大问题.针对上述不足,提出一种基于缓存映射项重用距离的地址映射方法IRR-FTL(inter-reference recency-based FTL),通过设置映射页缓存槽,充分挖掘负载空间局部性;基于缓存映射项重用距离实现负载自适应的写缓存映射表冷热分区,并分别采取不同的管理策略,减少映射页写操作;此外,实现基于重用距离的冷热数据分离存储,提高垃圾回收效率.通过采用多种负载对该方法进行验证实验,实验结果表明IRR-FTL相比DFTL缓存命中率提高29.1%,平均响应时间降低了27.3%,擦除次数降低了10.7%.

关键词: NAND闪存, 闪存转换层, 地址转换, 重用距离, 数据分离

Abstract: Demand-based flash translation layer(DFTL), which is a classical FTL address mapping method, solves the contradiction between large amounts of mapping information and limited cache capacity by only caching address mappings least recently used and leaving global mappings in flash memory. However, DFTL does not take full advantage of the spatial locality of workloads. When the cache is invalidated, dirty mapping entries will be swapped out frequently, causing lots of write operations of mapping pages. In addition, DFTL can’t address the problem of write amplification caused by valid page migration operations during garbage collection. In this paper, we propose a novel FTL address mapping method named IRR-FTL, which is based on inter-reference recency (IRR) of mapping entries. Firstly, IRR-FTL makes the most of the spatial locality of workloads by setting cache slots for translation pages. Secondly, IRR-FTL can make workloads adaptively write cache mapping table partitions based on IRR of mapping entries, which can reduce write operations of translation pages. Finally, IRR-FTL achieves hot and cold data separation, which can improve garbage collection efficiency. Compared with DFTL, our experimental results with a variety of workloads show that IRR-FTL can increase cache hit rate, average response time and erase counts by 29.1%, 27.3% and 10.7%, respectively.

Key words: NAND flash memory, flash translation layer (FTL), address translation, inter-reference recency, data separation