Abstract: To improve the performance of cipher processor, the performance model of cipher processor is proposed. And based on this model, three ways for enhancing cipher processor's performance are presented, which are sharing multi-level resources, binding operations of pre-xor or post-xor and maximizing parallelism of block cipher algorithms. According to these improvement methods, the type and amount of cryptographic function units are determined. However, the function units are not only numerous but also different in operation data width and latency, so how to organize these function units efficiently becomes a key problem. The stream processor architecture can integrate a large number of function units to obtain high performance. Then, we design and implement a reconfigurable block cipher processor prototype which is based on stream processor architecture, and in order to organize the numerous function units effectively, the function units are divided into basic units, inter-bank-shared units and inter-cluster-shared units respectively according to their processing width. The prototype is synthesized in 65nm CMOS process and several typical block cipher algorithms are mapped on it. The evaluation results show that the processor prototype is area-efficient and its performance is not only beyond that of international application specific instruction cipher processors, but also higher than that of the domestic reconfigurable array processors.