Abstract: With the exponential increase in the transistors per chip, microprocessors are becoming more susceptible to soft errors. Control flow checking has been proved effective in promoting soft error tolerant ability of microprocessors. The conventional control flow checking method inserts large number of signature instructions in the program by compiler. So it imposes large overheads on both binary code size and program execution performance. Moreover, the conventional control flow checking method does not consider the recovery from control flow errors. A new method, control flow checking and recovering by compiler signatures and hardware checking (CFCCH), is proposed in this paper to solve the aforementioned problems. CFCCH uses a compiler to insert signature data, not signature instructions, in the program to reduce the binary code size. Hardware checking is automatically triggered after the branch/jump instruction so that the execution cycles of the checking operation can be reduced. Hardware implemented context saving and recovering is also proposed to provide fast recovering from control flow errors. CFCCH based on 8051 architecture is implemented in this paper. Random faults are injected in the 8051 microcontroller with CFCCH to evaluate the soft error tolerant ability. The experimental results demonstrate that compared with the conventional control flow checking method, CFCCH can efficiently reduce the binary code size and program execution time while keeping the same soft error tolerant ability.