Racetrack memory (RM) is a competitive emerging non-volatile memory technology for future memory designs. It achieves ultra-high storage density by integrating multiple bits into a tape-like nanowire (called racetrack) and provides fast access speed. In order to access required bits in RM, a unique shift operation is introduced. However, it has been observed that the shift operation requires higher current than read and write operations and causes significant amount of energy dissipation, which degrades reliability and performance or even destroys RM cells. However, there still lacks an analytical thermal model to estimate run-time temperature of RM. More important, corresponding architecture level management schemes are needed to avoid thermal emergency that violates the constraint of peak temperature. In this work, we first propose a thermal model to explore relationship between temperature and design parameters. At the same time, in order to improve thermal reliability, we propose a quota-based shift management scheme to ensure the intensity of shift operations which is constrained under a specific threshold. Experiments show that the temperature increase is limited in 20℃ with only 3.5% performance degradation.