ISSN 1000-1239 CN 11-1777/TP

Journal of Computer Research and Development ›› 2018, Vol. 55 ›› Issue (5): 1065-1077.doi: 10.7544/issn1000-1239.2018.20170254

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FTL Address Mapping Method Based on Mapping Entry Inter-Reference Recency

Zhou Quanbiao, Zhang Xingjun, Liang Ningjing, Huo Wenjie,Dong Xiaoshe   

  1. (Department of Computer Science and Technology, Xi’an Jiaotong University, Xi’an 710049)
  • Online:2018-05-01

Abstract: Demand-based flash translation layer(DFTL), which is a classical FTL address mapping method, solves the contradiction between large amounts of mapping information and limited cache capacity by only caching address mappings least recently used and leaving global mappings in flash memory. However, DFTL does not take full advantage of the spatial locality of workloads. When the cache is invalidated, dirty mapping entries will be swapped out frequently, causing lots of write operations of mapping pages. In addition, DFTL can’t address the problem of write amplification caused by valid page migration operations during garbage collection. In this paper, we propose a novel FTL address mapping method named IRR-FTL, which is based on inter-reference recency (IRR) of mapping entries. Firstly, IRR-FTL makes the most of the spatial locality of workloads by setting cache slots for translation pages. Secondly, IRR-FTL can make workloads adaptively write cache mapping table partitions based on IRR of mapping entries, which can reduce write operations of translation pages. Finally, IRR-FTL achieves hot and cold data separation, which can improve garbage collection efficiency. Compared with DFTL, our experimental results with a variety of workloads show that IRR-FTL can increase cache hit rate, average response time and erase counts by 29.1%, 27.3% and 10.7%, respectively.

Key words: NAND flash memory, flash translation layer (FTL), address translation, inter-reference recency, data separation

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