ISSN 1000-1239 CN 11-1777/TP

Journal of Computer Research and Development ›› 2021, Vol. 58 ›› Issue (6): 1166-1175.doi: 10.7544/issn1000-1239.2021.20210174

Special Issue: 2021计算机芯片关键技术前沿与进展专题

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Design and Implementation of Configurable Cache Coherence Protocol for Multi-Core Processor

Chen Zhiqiang, Zhou Hongwei, Feng Quanyou, Deng Rangyu   

  1. (College of Computer Science and Technology, National University of Defense Technology, Changsha 410073)
  • Online:2021-06-01
  • Supported by: 
    This work was supported by the Foundation of the Key Laboratory of Defense Technology for Parallel and Distributed Processing (WDZC20205500117).

Abstract: In multi-core system, it is necessary to maintain the consistency of cache. Common cache coherence protocols can be divided into snoop-based protocol and directory-based protocol. Directory-based protocol has better scalability, lower latency and can be applied to more applications. According to the size of the directory, it can be divided into centralized directory and distributed directory. Distributed directory takes up less space and less time to inquiry. However, it’s hard to design and verify cache coherence based on distributed directory. To reduce the risk in designing CPU, a configurable distribute directory unit (CDDU) is proposed. It increases the flexibility and fault tolerance of the multi-core system by the way of changing state transformation and protocol flow. The special design can protect system from design defects that may lead to severe error, and it shows good performance in dealing with deadlock problems caused by cache coherence. It provides considerable fault-tolerance that can give the designer more freedom and opportunity. The simulation result indicates that it provides considerable scalability and prevents the occurrence of potential deadlock at the cost of subtle performance loss and area expense. The methodology mentioned in this paper has been used in the design of 64-core FT processor,which ensures the correctness of cache coherence protocol without totally modifying the initial design.Moreover, it improves the robustness of the protocol and eliminates the potential deadlock with a subtle impact on system performance.

Key words: multi-core processor, coherence protocol, configurable, fault-tolerance, deadlock

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