Approach to Analyze the Relationship of High-Level Fault Models

With the development of integrated circuit design, the traditional test done at gate level is proved to be time-consuming. It's necessary to test circuit at high level. Unfortunately, there are no effective fault models defined at high level. To solve this problem, two kinds of relationships between different fault models are analyzed. The relationship between a high level fault model and the stuck-at fault model(defined at gate level) is analyzed, followed by the analysis of relationship between two high level fault models. These relationships are expected to found one or a set of effective high-level fault models. High-level fault models founded are expected to direct ATPG(automatic test pattern generation) and DFT(design for test) more effectively than traditional ones. Two rules are defined to evaluate the high-level fault models. The induction is used to find these relationships in theory. According to the method presented, if test patterns generated by one high-level fault model can detect more detectable stuck-at fault models defined at gate level than other fault models, it is proved to be more effective. The experiment conducted on benchmark of ITC99 demonstrates this approach. Three kinds of high-level fault models are analyzed, which are the transfer fault model, the states fault model, and the branch fault model.