VLSI Design and Implementation of a High-Speed Viterbi Decoder

Based on an optimized structure, a high-speed (2,1,7) Viterbi decoder with trace-back length of 64 is presented in this paper. Considering the punctured convolutional codes for Viterbi decoding and the hardware complexity of its implementation, a modified ACS (add-compare-select) unit is used to satisfy its decoding requirements and reduce its hardware complexity. Also, a parallel structure is adopted to meet the working speed requirements but does not increase its hardware complexity. In order to increase its decoding throughput rate, the decoder employs blocked cyclic memory, which is composed of register file that can help reduce the implementation size of the decoder. A new trace-back unit is introduced to improve the way of data reading and writing for trace-back. Implemented by SMIC 0.18μm standard CMOS technology, its hardware scale is about 28 683 gates (2 input NAND is counted as a gate), and the highest speed is about 180MHz. Compared with other reported schemes, the performances of this proposed Viterbi decoder are better in terms of implementation size, throughput rate and constraint length. With the above excellent performances, the proposed Viterbi decoder is very suitable to be applied in the field of digital communication, which needs high throughput rate and small implementation size, such as DTV and HDTV.