VLSI Implementation of Multi-Standard LDPC Decoder Based on SIMD Architecture

Recently the LDPC decoder that could support multi-standard has become a major topic in the research of wireless communication system. Compared with traditional LDPC decoders, the proposed design in this paper has several merits as follows: 1.the novel decoder achieves a reconfigurable architecture for multiple code rates and data lengths, which consequently could support multi-standard schemes; 2.using a modified TPMP algorithm, the decoder largely reduces the memory size and avoids the data collision as a result of unstructured block-LDPC codes; 3.an architecture based on SIMD processor structure has been adopted to implement a high regular architecture which is convenient for chip layout; 4.enhancing the hardware resources utilization and gaining a higher system throughput by designing a dynamically reconfigurable 6-stage pipelined processing unit that can be configured into CNUs or VNUs by time-division multiplexing. A multi-standard LDPC decoder which supports both CMMB and DTMB standards has been synthesized on SMIC 0.13μm 1.2V 8-metal layer CMOS technology, the area of the decoder is about 0.75 million equivalent gates and the maximum operating clock frequency is 220MHz resulting in a decoding throughput of 300Mbps. The proposed architecture can be applied to other multi-standard LDPC decoder schemes, such as an integration of IEEE 802.16e (WiMAX) and IEEE 802.11n (WLAN), etc.