An on-Chip Dynamic Virtual Channel Router Based on Two-Step Flow Control Method

The on-chip area and power are limited seriously, so as to the capacity of packet buffer. So one of key issues of NoC design is how to use packet buffer efficiently. Dynamic virtual channel buffer is one of efficient ways, but may make congestion heavier, or even may make dead congestion appear. This paper proposes an on-chip dynamic virtual channel (DAVC) router based on two-step flow control method, which splits a packet into a head and a body to apply flow control algorithms separately, and it can retard congestion and stop dead congestion. There is a centralized share buffer on every input port in the router. The centralized share buffer is dynamic allocated to every packet of this input port according to the conditions of traffic and flow control, and can implement zero cycle delay between a read and a write and support variable packet length. The router also uses a two-level crossbar arbitrator and a novel virtual channel allocator based on tree, which allocates output virtual channel dynamically. The experiment results show that, compared with static virtual channel (SAVC), DAVC router provides 23.2% throughput improvement and 27.2% delay reduction with same buffer capacity, and provides 28.3% area and 23.8% power savings while having similar performance with half buffer capacity.