ISSN 1000-1239 CN 11-1777/TP

Journal of Computer Research and Development ›› 2021, Vol. 58 ›› Issue (6): 1230-1233.doi: 10.7544/issn1000-1239.2021.20210176

Special Issue: 2021计算机芯片关键技术前沿与进展专题

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DMR: An Out-of-Order Superscalar General-Purpose CPU Core Based on RISC-V

Sun Caixia, Zheng Zhong, Deng Quan, Sui Bingcai, Wang Yongwen, Ni Xiaoqiang   

  1. (College of Computer Science and Technology, National University of Defense Technology, Changsha 410073)
  • Online:2021-06-01
  • Supported by: 
    This work was supported by the Key-Area Research and Development Program of Guangdong Province (2019B121204007).

Abstract: DMR is a RISC-V based out-of-order superscalar general-purpose CPU core from the College of Computer Science and Technology, National University of Defense Technology. Three privilege levels, user-mode, supervisor-mode and machine-mode, are all supported, and the standard RISC-V RV64G instruction set is implemented. In addition, custom vector instructions are extended in DMR. Sv39 and Sv48 are supported for the virtual-memory system, and the size of physical address is 44-bit. The pipeline for single-cycle integer instructions is 12-stage in all. All instructions are executed out of program order and committed in program order. More than four instructions can be issued per cycle. Distributed schedule queues are used and at most 9 instructions can be out-of-order scheduled for executions in one cycle. Multi-layer, multi-platform functional verification method driven by functional coverage is used, and Linux OS is already booted on FPGA prototype system. DMR reaches 5.12CoreMarkMHz and targets 2GHz clock speed in 14nm technology.

Key words: RISC-V, out-of-order, superscalar, CPU core, general-purpose CPU

CLC Number: