Review of Chiplet Interconnection Technology

Wang Hao; Wang Yong; Feng Changlei; Gai Weixin; Wu Peng; Qian Jiang

doi:10.7544/issn1000-1239.202440585

Journal of Computer Research and Development > 2025 > Accepted Manuscript > DOI: 10.7544/issn1000-1239.202440585 CSTR: 32373.14.issn1000-1239.202440585

Wang Hao, Wang Yong, Feng Changlei, Gai Weixin, Wu Peng, Qian Jiang. Review of Chiplet Interconnection Technology[J]. Journal of Computer Research and Development. DOI: 10.7544/issn1000-1239.202440585

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Review of Chiplet Interconnection Technology

Wang Hao^{1, 2,},
Wang Yong^2, ,,
Feng Changlei²,
Gai Weixin¹,
Wu Peng²,
Qian Jiang^{1, 2}

1.
School of Integrated Circuits, Peking University, Beijing 100871
2.
Beijing Microelectronics Technology Institute, Beijing 100076

More Information

Author Bio:
Wang Hao: born in 1993. PhD, engineer. His main research interests include Chiplet interconnection, digital signal processing and VLSI implementation

Wang Yong: born in 1977. PhD, professor. His main research interests include Chiplet and integrated chip design and testing, manufacturing process, packaging, testing, detection, and failure analysis of integrated circuits and semiconductor discrete devices

Feng Changlei: born in 1984. PhD candidate, professor. His main research interests include Chiplet interconnection and integration, microsystem design and testing

Gai Weixin: born in 1969. PhD, professor. His main research interests include ultra-high-speed wireline transceiver, Chiplet interface circuits, optical receiver, phase-locked loop, and high-speed analog-to-digital converter

Wu Peng: born in 1988. Master, senior engineer. His main research interests include heterogeneous integration design, signal integrity and power integrity research

Qian Jiang: born in 1994. PhD, engineer. His main research interests include 2.5D integration design and interconnection structure design
Received Date: June 30, 2024
Revised Date: February 17, 2025
Accepted Date: March 02, 2025
Available Online: March 02, 2025

Graphical Abstract

Abstract

Abstract

As the breaker of Moore’s Law, Chiplet technology has high expectations in the integrated circuit industry. Chiplet technology can combine multiple small chips with specific functions into a Chiplet integrated chip through high-speed interconnection technology, whose core technology is the Chiplet interconnection technology that can achieve Chiplet combination and expansion. This paper analyzes and discusses the Chiplet interconnection protocol, interconnection architecture, typical interconnection Chiplets, and testability design based on the interconnection Chiplet. Firstly, this paper provides a detailed comparison and analysis of domestic and foreign Chiplet interconnection protocols, and provides the layers and functions of each protocol. Secondly, this paper introduces three typical Chiplet interconnection architectures, and analyzes the characteristics and advantages of each architecture. Afterwards, the Chiplet fault-tolerant mechanism is introduced, including fault-tolerant encoding of interconnection interfaces, fault-tolerant topology, and fault-tolerant routing. Then, three types of interconnection Chiplet design schemes are presented, including programmable interconnection Chiplets, path programmable interconnection Chiplets, and fully customized interconnection Chiplets. Finally, a testability design testing scheme based on the interconnection Chiplet is introduced. This paper focuses on Chiplet interconnection and aims to help readers help readers have a systematic understanding of Chiplet interconnection technology.
- Chiplets,
- interconnection,
- interconnection Chiplets,
- architecture,
- fault tolerance,
- design for testability

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References (43)

References

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