The Synthesis of Multiple Stateful Logic Gates for In-memory Computing with Low Wear

Zhao Anning; Xu Nuo; Liu Kang; Luo Li; Pan Bingzheng; Bo Ziyi; Tan Chenghao

doi:10.7544/issn1000-1239.202440627

Journal of Computer Research and Development > 2025 > 62(3): 620-632. > DOI: 10.7544/issn1000-1239.202440627 CSTR: 32373.14.issn1000-1239.202440627

Zhao Anning, Xu Nuo, Liu Kang, Luo Li, Pan Bingzheng, Bo Ziyi, Tan Chenghao. The Synthesis of Multiple Stateful Logic Gates for In-memory Computing with Low Wear[J]. Journal of Computer Research and Development, 2025, 62(3): 620-632. DOI: 10.7544/issn1000-1239.202440627

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The Synthesis of Multiple Stateful Logic Gates for In-memory Computing with Low Wear

Zhao Anning^1,,
Xu Nuo^{1, 2, ,},
Liu Kang¹,
Luo Li^{1, 2},
Pan Bingzheng¹,
Bo Ziyi¹,
Tan Chenghao¹

1.
School of Computer Science and Technology, National University of Defense Technology, Changsha 410073
2.
Key Laboratory of Advanced Microprocessor Chips and Systems (National University of Defense Technology), Changsha 410073

Funds: This work was supported by the National Natural Science Foundation of China (62202483), the Hunan Provincial Natural Science Foundation of China (2022JJ40563), the Open Project Program of Wuhan National Laboratory for Optoelectronics (2021WNLOKF019), and the Open Fund of PDL (WDZC20235250112).

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Author Bio:
Zhao Anning: born in 2001. Master candidate. Student member of CCF. His main research interest includes automation of in-memory stateful logic

Xu Nuo: born in 1989. PhD, assistant researcher. Senior member of CCF. His main research interests include emerging non-volatile memory technologies (e.g. ReRAM /memristor) and their employment in in-memory computation

Liu Kang: born in 2001. Master candidate. Student member of CCF. His main research interests include memristor stateful logic, in-memory computing

Luo Li: born in 1971. PhD, research fellow. Member of CCF. Her main research interest includes high-performance general-purpose microprocessor design and verification technology

Pan Bingzheng: born in 1999. PhD candidate. Student member of CCF. His main research interests include the applications of memristor technology and memristor-based convolutional neural network computing

Bo Ziyi: born in 2001. Master candidate. Student member of CCF. Her main research interest includes in-memory computing

Tan Chenghao: born in 2002. Master candidate. Student member of CCF. His main research interests include the applications of memristor technology and memristor-based convolutional neural network computing
Received Date: July 19, 2024
Revised Date: January 16, 2025
Available Online: January 19, 2025

Graphical Abstract

Abstract

Abstract

By merging the functions of Boolean logic and non-volatile memory, memristive stateful logic can achieve the real sense of in-memory computing through eliminating data movement during computation, which breaks the “memory wall” and “energy wall” of traditional von Neumann computing system. In recent years, a series of the memristor-based in-memory stateful logic gates have been proposed by linking the conditional switching process and mathematical logic function, whose functions cover multiple logic functions such as IMP, NAND, NOR, and NIMP etc. However, the automated synthesis and mapping method for implementing the in-memory complex stateful logic computation by cascading the stateful logic gates is still embryonic, especially lacking the investigations on the device wear, which limits the application of in-memory stateful logic in edge computing scenarios. To reduce the device wear (toggle rate) in a complex in-memory stateful logic computation process, we propose a stateful logic synthesis and mapping process based on multiple stateful logic gates for low-wear in-memory computing. Compared with the two state-of-art stateful logic synthesis and mapping tools of SIMPLER MAGIC and LOSSS, the proposed low-wear logic synthesis and mapping process achieves an average improvement of over 35.55% and 8.48% in the toggle rates respectively under the EPFL combinational benchmark circuits. Moreover, the proposed tool achieves an average improvement of over 47.26% and 6.72% in the toggle rates respectively under the LGSynth91 benchmark circuits.
- memristor,
- stateful logic,
- toggle rate,
- logic synthesis and mapping,
- low wear

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References (33)

References

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