Bus-Invert Encoding Oriented Low Power Scheduling Method

Power consumption is an important aspect in the design of embedded systems. Aiming at the bus power consumption and balance usage that is one of the most important parts of total power, we propose a low power instruction scheduling method that orients to the bus-invert encoding. It can greatly improve the efficiency of bus-invert encoding. First, the method helps with the profile tool such as sim-profile to pick out the branch access frequencies of the program. And then the data random enhancement scheduling instruction (DRESI) is proposed to schedule the instructions for both entry instruction and intra instructions in basic block, which is guided by the branch frequencies information. It can not only reduce the frequency of the total bus inverts, but also balance the inverts between buses. Our experiments evaluated by the test cases of MiBench benchmark show that the method obtains considerable reduction in bus invert and more balance between buses. It can get about 26% on average bus invert reduction compared with original sequence of GCC with the two level (-O2) optimization and more than 10% reduction compared with the VSI+BI method. And furthermore, in the utilization balance of bus inverts, it also gets about 14.4% improvements on average.