State Vector Selective Generation of Parallel Folding Counters

Test pattern generation has a significant impact on the efficiency of built-in self-test (BIST) of integrated circuits. The existing parallel folding counters can only implement sequential state vector folding calculation, resulting in generating a large number of redundant test patterns and hindering its application in BIST test generation. In this paper, a parallel folding counter (PFC) that supports state vector selective generation is proposed, in which an original flip control vector (FCV) is introduced to establish the internal logic relation between the folding distances and FCVs. A given folding distance (FD) is decoded by the bit replacement control logic to control bit replacement for the original FCV with the lowest bit of the folding distance, producing a FCV that is then used to perform XOR operation with the folding seed vector, generating the selected state vector, where the bit replacement control logic can be designed recursively with folding distance increasing. Theoretical analysis and experimental results show that compared with the existing schemes, the proposed folding counter can be used to generate anyone of all the n+1 state vectors corresponding to a given n-bits of seed vector, which reduces BIST deterministic test set generation time significantly, while keeping comparable hardware overhead with the existing parallel folding counters.