A Programmable Data Plane Design in Computer Architecture

With the development of the Internet and cloud computing, more and more applications are migrated from local host to the cloud. In the cloud computing environment, these applications will finally be deployed to run in data centers, with the sharing of computer infrastructures. Influenced by the complexity and the variability of the applications running in data center, some fixed-function hardware components in traditional computer architecture, such as last-level cache, memory controller, I/O controller, can not meet the requirements of deploying these application together in one data center. To adapt to these dynamic requirements, programmable hardware is needed from the view of computer architecture level, to make the function of computer hardware adaptable according to the application requirements. A programmable data plane design for computer architecture is presented, which brings programmability to hardware components by integrating programmable processors into the state-of-the-art hardware components, and let these new processors process hardware requests by firmware code. The functions of hardware components can be extended by updating firmware running on the processors. An FPGA prototype is implemented. Evaluation results show that the programmable data plane design brings flexible programmability to hardware by reasonable resource consumption, without introducing too much overhead to the original system performance. This makes it possible for the computer hardware to adapt to the dynamic requirement of application running in data centers.