Practice of Chip Agile Development: Labeled RISC-V

Current chip design projects require considerable manpower and time to carry out, and have certain risks. These conditions have limited the development of open-sourced chip design to some extent. To further reduce the threshold for chip development, research teams at University of California, Berkeley have designed the open ISA RISC-V. They also open-sourced the Rocket Chip project, the SoC implementation of RISC-V, and put forward Chisel, a new hardware construction language, for agile development. How do RISC-V, Rocket Chip and Chisel enable open-source chip agile development? With some case studies during the development of the Labeled RISC-V project led by the Institute of Computing Technology, Chinese Academy of Sciences, this article shows: 1) An open and active ISA ecosystem (such as RISC-V) is a necessary condition to promote chip innovation; 2) Chisel’s features such as bulk connection, metaprogramming, object-oriented programming, and functional programming, can greatly reduce the amount of code and improve code maintainability; 3) Agile development can achieve an order of magnitude improvement in coding efficiency, while achieving comparable or even better performance, power consumption and area overhead than traditional hardware development models.