ChipletNP: Chiplet-Based Agile Customizable Network Processor Architecture

In order to meet different requirements of performance, flexibility and quality of service in new network scenarios such as 5G and 8K video, network processor (NP) becomes increasingly complex and diverse. Traditional network processors try to integrate amount of heterogeneous processing resources such as processor cores, caches and accelerators on a single SoC (system on chip) to provide highly customizable capabilities. However, with the failure of Moore’s Law and Dennard’s scaling law, developing one-big network processor becomes unsustainable as it faces greater challenges in R & D cycle, cost and innovation iteration. We propose a novel agile customizable architecture for network processor, namely ChipletNP, which decouples heterogeneous resources and uses Chiplet technology to quickly customize new NPs by combining existing mature chip products. ChipetNP is highly flexible as it has an agile switching network which can connect diverse heterogeneous resources with high throughput and predictable delay. We develop a network processor chip, i.e., YHHX-NP, based on ChipletNP architecture, which integrates commercial CPU, FPGA (field programmable gate array) and agile switching chip. Our results show that ChipletNP supports various emerging network functions such as SRv6 (segment routing over IPv6) with ultra-low latency (<2.82 µs), and achieves more than two times energy efficiency improvement compared with commercial chips.