XiangShan Open-Source High Performance RISC-V Processor Design and Implementation

In recent years, the open-source instruction set architecture represented by RISC-V, has led the trend of open-source processors. However, the performance of these open-source processors is not enough to meet the needs of researchers in academia and developers in industry. To fill in the gap, we launch XiangShan project. XiangShan is an open-source high performance RISC-V processor. It features six-width-issue superscalar out-of-order design. XiangShan has earned over 3200 stars and 400 forks on the famous open-source hosting platform GitHub, becoming one of the most popular open-source hardware projects in the world. The project also receives great support from companies and researchers all around the world. XiangShan project has been developed for over two years with two stable generations. The first generation called Yanqihu micro-architecture has been successfully taped out, and the performance of the real chip is in line with our expectation. The second generation called Nanhu micro-architecture has entered the final optimization stage. It will be taped out soon. To the best of our knowledge, Nanhu micro-architecture achieves the highest performance among all open-source processors. This paper mainly introduces the first two generations of XiangShan processor, focusing on the design details and evolution of micro-architecture. The challenges and experiences during the development of XiangShan are discussed systematically.