HVMS: A Hybrid Vectorization-Optimized Mechanism of SpMV

Sparse matrix-vector multiplication (SpMV) plays an important role in a wide variety of scientific and engineering applications.Executing SpMV efficiently on vector processors is challenging because of the irregular memory access of sparse matrices.We conduct a detailed analysis of the main factors that impact the efficiency of SpMV vectorization.In addition to the irregular distribution of non-zero elements within sparse matrices, different sparse matrices also exhibit huge variations in the distribution characteristics of non-zero elements.Therefore, it is difficult to apply a universal vector optimization method for matrices with diverse characteristics.Furthermore, there is a big difference in vector computing and vector instructions for various vector processors.The primary challenge of SpMV vectorization lies in mapping the irregular sparse matrices onto the regular vector processor.In this paper, we propose a hybrid vectorization-optimized mechanism of SpMV(HVMS).HVMS models the characteristics of vector processors and designs corresponding rules based on the abstracted basic operations to guide the regularization conversion of sparse matrices.HVMS divides the matrix into different parts according to the different characteristics.For each part, the non-zero distribution can be less irregular and then introduce corresponding optimization mechanisms to boost the vectorization efficiency of SpMV.We implement and evaluate HVMS on an Intel Xeon processor and compare it with three state-of-the-art approaches using 30 sparse matrices.Experimental results show that HVMS can achieve an average speedup of 1.60x, 1.72x, and 1.93x over CVR, SELL-C-σ, and Intel MKL, respectively.