FireLink: An Evaluation Framework for Chiplet Design Space Exploration

Li Kai; Zeng Kun; Rong Peitao; Chen Zhiqiang; Zhang Tian; Wang Yongwen

doi:10.7544/issn1000-1239.202440082

Journal of Computer Research and Development > 2025 > 62(5): 1108-1122. > DOI: 10.7544/issn1000-1239.202440082 CSTR: 32373.14.issn1000-1239.202440082

Li Kai, Zeng Kun, Rong Peitao, Chen Zhiqiang, Zhang Tian, Wang Yongwen. FireLink: An Evaluation Framework for Chiplet Design Space Exploration[J]. Journal of Computer Research and Development, 2025, 62(5): 1108-1122. DOI: 10.7544/issn1000-1239.202440082

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FireLink: An Evaluation Framework for Chiplet Design Space Exploration

College of Computer Science and Technology, National University of Defense Technology, Changsha 410073
Key Laboratory of Advanced Microprocessor Chips and Systems (National University of Defense Technology), Changsha 410073

Funds: This work was supported by the TDRCJH Program (22-TDRCJH-02-006), the National Natural Science Foundation of China for Young Scientists (NSFC-62202481), and the Research Program of National University of Defense Technology (ZK22-05)

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Author Bio:
Li Kai: born in 2000. PhD candidate. His main research interests include microprocessor architecture design and chip design space exploration

Zeng Kun: born in 1983. PhD, associate professor. Member of CCF. His main research interests include microprocessor architecture and parallel computing

Rong Peitao: born in 2000. Master candidate. His main research interests include microprocessor architecture design and FPGA accelerated simulation

Chen Zhiqiang: born in 1998. PhD candidate. His main research interests include microprocessor architecture design and network on chip

Zhang Tian: born in 1999. Master candidate. Her main research interest includes general sparse matrix multiplication

Wang Yongwen: born in 1977. PhD, professor. Senior member of CCF. His main research interests include processor microarchitecture, and high performance computing
Received Date: February 01, 2024
Revised Date: October 10, 2024
Accepted Date: October 14, 2024
Available Online: October 21, 2024

Graphical Abstract

Abstract

Abstract

The Chiplet-integrated chip based on advanced packaging technology offers a number of advantages in terms of manufacturing cost, design efficiency and special customization, etc. We represent a new and effective method of maintaining the performance growth of the chip in the post-Moore era. As an important method of quantitative analysis of architectural design, design space exploration (DSE) can assist designers in comprehending and evaluating the intricate interrelationships between design parameters. However, when applying the traditional DSE method directly to the Chiplet design, it gives rise to issues such as incomplete evaluation, inaccurate simulation, and low efficiency. The solution to these problems is FireLink, an evaluation framework for Chiplet design space exploration. FireLink supports the modelling and simulation of Chiplet microarchitectures and interconnection networks, and is capable of efficiently evaluating performance, power, area and cost metrics. Furthermore, experiments are conducted using ID3 (iterative dichotomiser 3) machine learning algorithm in this framework, which has been demonstrated to effectively improve the efficiency of DSE. In comparison with existing DSE methodologies, FireLink exhibits notable advantages in comprehensiveness of evaluating, completeness of modeling and efficiency of DSE, therefore designers can explore a wider range of design space in a shorter time, so as to select a better Chiplet design scheme.
- Chiplet,
- design space exploration,
- simulation,
- evaluation,
- microarchitecture

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References (61)

References

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