Faver: Function-Abstracted Verification for RTL Generation with ReAct Reasoning

Register Transfer Level (RTL) code generation based on large language models (LLMs) has emerged as a promising research direction, as it targets the least automated stage in current chip design workflows. However, the substantial semantic gap between high-level specifications and RTL, combined with limited training data, poses significant challenges for generation accuracy. A natural approach is to leverage human design experience by integrating design and verification, yet RTL test data are even scarcer than design data, making this strategy less LLM-friendly. In contrast, LLMs exhibit stronger capabilities in high-level languages such as Python or C, which are more suitable for functional specification and appear promising for RTL verification. Nevertheless, a large semantic gap remains, with notable differences in spatiotemporal granularity between high-level languages and hardware code. Verifying RTL using Python or similar high-level languages requires the LLM not only to understand high-level functional semantics but also to ensure that low-level timing and operational details match the circuit behavior, which is nontrivial. To address this challenge, we propose Faver: Function-Abstracted Verification for RTL Generation with ReAct Reasoning, a middleware framework that streamlines RTL verification in LLM-based workflows. By combining LLM-friendly code structures with rule-based templates, Faver decouples circuit verification details, enabling the LLM to focus on functionality itself. Experimental results on both SFT and open-source models show that Faver can improve RTL generation accuracy by up to 14%.