Quantitative Evaluation of the Cryptographic Block’s Resistibility to Power Analysis Attack at Different Design Level

In the design and implementation of cost effective and power-analysis-resistant secure chip, it is necessary to perform quantitative analysis of the cryptographic block’s ability to prevent power analysis attack. The key of quantitative analysis is to evaluate the resistibility to power analysis attack and simulate the instantaneous power trace. The number of power samples required to perform power analysis attack successfully is used to characterize the resistibility. The number of samples is computed based on the signal-to-noise ratio of the corresponding power analysis attack. In order to compute the number of power samples, it is necessary to simulate the instantaneous power trace of cryptographic blocks. The instantaneous power trace is expressed as a discrete time sequence of instantaneous current, not the average power consumption or the peak power consumption. A method is presented to simulate the cryptographic block’s instantaneous power trace through the design cycle including RTL(register transfer level) design, synthesis and place & route. Two kinds of speedup methods which are the time reduction at the cost of space and the multi-thread parallel simulation are proposed. So that the simulation can be speeded up, and also be applicable to power trace simulation of large scale circuits.