Coarse-Grained Dataflow Network Processor：Architecture and Prototype Design

Network processors (NPs) are programmable, highly integrated communications circuits optimized to support packet processing and forwarding at high rate. As an important component of routers, the design of network processors addresses the requirement of high performance while maintaining the flexibility to accommodate the future network protocols. Aimed at the limitation of ILP exploitation and the fixed topology of control-flow NP, a novel scheme and prototype of coarse-grained dataflow NP architecture—DynaNP is proposed. DynaNP not only improves the programmability of the entire NP by utilizing the control-flow structure of each processing element (PE), but also effectively exploits the task-level parallelism by introducing data-flow model into the processing among the PEs. A mechanism of dynamic configurable processing path is also provided in DynaNP to improve the overall throughput of the system. Moreover, the prototype system of DynaNP is introduced in this paper. The prototype system is designed based on SoPC (system on programmable chip). Multiple PEs and several functional modules are connected by on-chip communication network. The PEs are implemented by utilizing the embedded RISC processor core LEON3. And, the instruct-set of the LEON3 is extended to accelerate the processing of network protocols. The basic functions and the key techniques of DynaNP can be investigated through the prototype system.