Performance Analysis of the 2-D Networks-on-Chip

The interconnection networks-on-chip becomes an important factor affecting the performance of chip-multiprocessor. Almost all interconnection structures evolve from the 2-D networks. After analyzing the static networks characteristics of some popular 2-D interconnection networks-on-chip whose inner-nodes degree is 4, the authors propose a kind of interconnection networks-on-chip router and the communication protocol. The router uses buffers just on the outside port rather than on both the inside and the outside port to reduce the power and increase the speed in the networks transmission. Based on the analysis of the dynamic networks characteristics of those different structures by changing the scales and the loads, load per cost-delay product, a new evaluation to the all-sided performance of interconnection networks-on-chip, is proposed using the link to indicate the cost. Finally, the all-sided performance of those different 2-D interconnection networks-on-chip structures is analyzed and the suitable cases for each structure is indicated. The experimental results show that in the case of small-scale under low-load the multi-ring networks do well and in the case of larger-scale under larger load mesh grids work better. The wrap around structures is the first choice as long as it could be. However, in the case of large-scale, it is difficult to get good performance by just adopting any one of those structures directly.