Optimized Software-Hardware Communications for Shared Memory Reconfigurable Computer

Hardware processes and hardware centric execution model introduced by BORPH have improved the usability of reconfigurable computers significantly. BORPH-N is designed as an extended system of BORPH. The main extension is that BORPH-N supports shared memory reconfigurable computers. And hardware processes can communicate with the rest of the system by shared memory and semaphore which are Unix semantic in BORPH-N. Accelerating the computing intensive parts of applications is one of the most important goals of reconfigurable computing. Thereby efficiency of software-hardware communications is very crucial. Supporting shared memory and semaphore through simple mechanisms such as remote system call, can definitely not meet the need of applications. Independent-execution-based optimizations are adopted by BORPH-N. Independent execution means the FPGA does some work locally without the help of the host. The efficiency will be enhanced a lot due to the elimination of data exchange between the host and FPGA. To reduce the workload, only the functions which are repeated frequently during the execution of applications will be completed by FPGA independently. BORPH-N focuses on two tasks: virtual memory access and atomic variable access. Experiment is setup on a PC with an ARRIA II GX FPGA board. The results show the hardware overhead of BORPH-N is low. The efficiency of shared memory and semaphore access is close to the peak performance of hardware platform.