• 中国精品科技期刊
  • CCF推荐A类中文期刊
  • 计算领域高质量科技期刊T1类
Advanced Search
Fang Yuejian, Shen Qingni, Wu Zhonghai. A Parallel Architecture for FPGA Based Hyperelliptic Curve Cryptoprocessor[J]. Journal of Computer Research and Development, 2013, 50(11): 2383-2388.
Citation: Fang Yuejian, Shen Qingni, Wu Zhonghai. A Parallel Architecture for FPGA Based Hyperelliptic Curve Cryptoprocessor[J]. Journal of Computer Research and Development, 2013, 50(11): 2383-2388.

A Parallel Architecture for FPGA Based Hyperelliptic Curve Cryptoprocessor

More Information
  • Published Date: November 14, 2013
  • Hyperelliptic curve is an extension of elliptic curve cryptography. Shorter key lengths of hyperellitic curve cryptosystems (HECC) can be used to achieve same level of security comparing to RSA and elliptic curve cryptosystem (ECC). A parallel architecture for field programmable gate array (FPGA) based hyperelliptic curve cryptoprocessor is designed in this paper. The processor is composed of parallel finite field (FF) cores, and each core consists of a control unit, a register file and an ALU. Through sharing mechanism of register files, the independent cores can collaborate to fulfill complicated computations. Each ALU can execute customized instruction A(B+C)+D, and the instruction can be flexibly configured in the instruction generation and execution process. In our architecture, since every ALU is coupled with a control unit and a ROM, the ALUs are independent of each other. Any ALU can be started at any cycle, so multiple instructions can run on ALUs at the same time. The results of ALUs can be shared among the register files, so multiple ALUs can cooperate to finish complicated computations. A four stage pipeline is used to increase performance. The architecture designed can sufficiently support parallel processing and much higher speed up has been gained with the experiment results.
  • Related Articles

    [1]Huang Shuangqu, Xiang Bo, Bao Dan, Chen Yun, and Zeng Xiaoyang. VLSI Implementation of Multi-Standard LDPC Decoder Based on SIMD Architecture[J]. Journal of Computer Research and Development, 2010, 47(7): 1313-1320.
    [2]Xu Long, Deng Lei, Peng Xiaoming, Ji Xiangyang, Gao Wen. The VLSI Design of AVS Entropy Coder[J]. Journal of Computer Research and Development, 2009, 46(5): 881-888.
    [3]Luo Zuying, Pan Yuedou. Transistor-Level Methodology on Power Optimization for CMOS Circuits[J]. Journal of Computer Research and Development, 2008, 45(4): 734-740.
    [4]Li Qing, Deng Yunsong, Zeng Xiaoyang, and Gu Yehua. VLSI Design and Implementation of a High-Speed Viterbi Decoder[J]. Journal of Computer Research and Development, 2007, 44(12): 2143-2148.
    [5]Wen Dongxin, Yang Xiaozong, and Wang Ling. A High Level Synthesis Scheme and Its Realization for Low Power Design in VLSI[J]. Journal of Computer Research and Development, 2007, 44(7): 1259-1264.
    [6]Zhao Jia, Zeng Xiaoyang, Han Jun, Wang Jing, and Chen Jun. VLSI Implementation of an AES Algorithm Resistant to Differential Power Analysis Attack[J]. Journal of Computer Research and Development, 2007, 44(3).
    [7]Wu Min, Zeng Xiaoyang, Han Jun, Ma Yongxin, Wu Yongyi, and Zhang Guoquan. A Low Cost RSA Chip Design Based on CRT[J]. Journal of Computer Research and Development, 2006, 43(4): 639-645.
    [8]Lan Xuguang, Zheng Nanning, Xue Jianru, Wang Fei, and Liu Yuehu. Low-Power and High-Speed VLSI Architecture Design of 2-D DWT/IDWT[J]. Journal of Computer Research and Development, 2005, 42(11): 1889-1895.
    [9]He Weifeng, Mao Zhigang, Lü Zhiqiang, and Yin Haifeng. VLSI Design for Full-Search Block-Matching Full-Pel Motion Estimation Processor[J]. Journal of Computer Research and Development, 2005, 42(7): 1225-1230.
    [10]Li Tiejun, Shen Chengdong, and Li Sikun. A VLSI Architecture for PMVFAST Block-Based Motion Estimation Algorithm[J]. Journal of Computer Research and Development, 2005, 42(4): 537-543.

Catalog

    Article views (891) PDF downloads (627) Cited by()

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return