A Low-Power Instruction Cache Design Based on Record Buffer

Most modern microprocessors employ on-chip caches to bridge the enormous speed disparities between the main memory and central processing unit (CPU), but these caches consume a significant fraction of total energy dissipation, especially the power dissipated by instruction cache itself is often a significant part of the power dissipated by the entire on-chip caches. Using buffer can filter most of instruction cache accesses and reduce it's power consumption, but there arestill many unnecessary data array accesses left, based on this idea. In this paper, a low-power instruction cache called RBC is proposed. With the record buffer and the modification on data array, RBC can filter most of the unnecessary cache activities, thus reducing energy consumption significantly. Experiments on 10 SPEC2000 benchmarks show that, compared with conventional block buffering cache, 24.33% energy savings for instruction cache can be achieved, at the cost of only 6.01% slowdown and 3.75% area overhead.