CIRCUIT OF CONVERTING INTEGER TO FLOATING-POINT AND ITS PERFORMANCE OF COMPLEMENTING AND ROUNDING IN PARALLEL AND ADAPTATION OF BIT LENGTH ITSELF

A new circuit design method is proposed, which implements conversions from integer numbers to floating-point numbers, and the correctness of the method is proved. By using this method, complementing and rounding are combined and processed in parallel, so that the critical path is 15 gate delays less than common circuit structure, and the circuit scale is decreased. Because of the decreased critical path delay, the conversion can be implemented in a single cycle. In addition, bit length is adapted by itself, so the conversions from long integer or integer numbers to single or double precision floating-point numbers can be implemented, with little cost of delay and scale. The method can be applied to the contrary conversion too. The module is simulated and verified by Fujitsu CE71 under 100MHz, and is adopted by the project.