Functional Units Design in Godson-2 Processor

The algorithm and its implementation of functional units are very vital for the performance of today's state of art general-purpose microprocessor design. An overview of the functional units design in Godson-2 processor is given and some details including architecture and physical design are described. Godson-2 has two fixed-point functional units: ALU1 and ALU2, and two floating-point units (FPU): FALU1 and FALU2. The MMX-like instructions are also implemented in Godson2 FPU. The FPU is IEEE-754 and MIPS compliant. The floating-point adder and multiplier have 4-cycle and 5-cycle latencies respectively, and the floating-point division has various 4~17 cycle latencies. The physical design based on the standard cell methodology with SMIC 0.18μm CMOS technology show that 2Gflops for single precision and 1Gflops for double precision performance are achieved with the speed of 500MHZ.