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    Hu Weiwu, Zhang Fuxin, and Li Zusong. Design and Performance Analysis of the Godson-2 Processor[J]. Journal of Computer Research and Development, 2006, 43(6): 959-966.
    Citation: Hu Weiwu, Zhang Fuxin, and Li Zusong. Design and Performance Analysis of the Godson-2 Processor[J]. Journal of Computer Research and Development, 2006, 43(6): 959-966.

    Design and Performance Analysis of the Godson-2 Processor

    • In this paper, the design and the result of performance analysis of the Godson-2 processor are presented. The Godson-2 implements a 4-way superscalar pipelined architecture, contains two 64KB L1 caches for instruction and data, and supports up to 8MB off-chip L2 cache. To improve the pipeline efficiency, The Godson-2 utilizes out-of-order executing technologies such as advanced branch prediction unit, register renaming and dynamic scheduler, and dynamic memory access mechanism like non-blocking cache and load speculation. The Godson-2 is implemented on 0.18um CMOS technology, with a maximum frequency of 500MHz under normal voltage and consumes 3-5 watts power under that frequency. The Godson-2 can perform one billion double-precision floating-point operations per second (two billion for single-precision), and the overall performance is comparable to Intel Pentium III with similar frequency. Presently a full Linux distribution (Debian) is running well on the Godson-2 prototype machines, including important desktop applications such as Mozilla web browsers, media players and OpenOffice.
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