A High Efficient Architecture for Motion Estimation Based on AVC/AVS Coding Standard

In the new video compression standards, AVC and AVS, the motion estimation adopts many new features such as variable block size searching, multiple reference frames, motion vector prediction, etc, for achieving superior coding performance. However, these new features greatly increase the computation complexity of the motion estimation. To satisfy the high computation requirement, a high efficient architecture is proposed for variable block size motion estimation (VBSME). It has two clocks, the slow clock and the fast clock. The former is used by the periphery of the architecture and the latter is used by the kernel of it. The kernel achieves very high frequency by adopting the fine-grained level for the pipeline implementation. And the pipeline also achieves very high efficiency. Experimental results show that this architecture has powerful computation capability of coding 720×576 picture size at 71fps with the search range of 65×65.