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Li Yong, Wang Lei, Gong Rui, Dai Kui, and Wang Zhiying. Research and Implementation of a 32-Bit Asynchronous Multiplier[J]. Journal of Computer Research and Development, 2006, 43(12): 2152-2157.
Citation: Li Yong, Wang Lei, Gong Rui, Dai Kui, and Wang Zhiying. Research and Implementation of a 32-Bit Asynchronous Multiplier[J]. Journal of Computer Research and Development, 2006, 43(12): 2152-2157.

Research and Implementation of a 32-Bit Asynchronous Multiplier

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  • Published Date: December 14, 2006
  • An asynchronous circuits design flow based on macrocell is presented in this paper. Being compatible with current EDA tools for synchronous design, this flow can decrease the difficulties of design and improve the efficiency as well. Based on this flow, a 32-bit asynchronous multiplier in 0.35μm process is designed. Compared with the synchronous multiplier of the same data path, the asynchronous multiplier has the similar performance but with smaller area size and lower power dissipation.

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