Research and Implementation of a 32-Bit Asynchronous Multiplier

An asynchronous circuits design flow based on macrocell is presented in this paper. Being compatible with current EDA tools for synchronous design, this flow can decrease the difficulties of design and improve the efficiency as well. Based on this flow, a 32-bit asynchronous multiplier in 0.35μm process is designed. Compared with the synchronous multiplier of the same data path, the asynchronous multiplier has the similar performance but with smaller area size and lower power dissipation.