Adaptive Stack Cache with Fast Address Generation

With the processor-memory performance gap continuing to grow, the performance of memory access becomes the major bottleneck of the performance improvement for modern microprocessors. Adaptive stack cache with fast address generation policy is proposed by investigating memory access behavior of programs. Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction-level parallelism, reduces data cache pollution and decreases data cache miss rate. Stack access latency can be reduced by using fast address generation scheme proposed here. Adaptive stack cache with fast address generation policy can also avoid unnecessary memory traffic. Stack cache can be disabled adaptively, when it is overflown. It can also be applied to multithread scheme by adding thread identifier. The results obtained indicate that about 25.8% of all memory reference instructions in SPEC CPU2000 benchmarks are executed in parallel by adopting adaptive stack cache with fast address generation. On average 9.4% data cache miss is reduced. The performance is improved significantly. The average IPC speedup is 6.9%.