Research on Real-Time Realizing PGA Algorithm in FPGA

Synthetic aperture radar (SAR) image has some common features such as huge data volume, relative complex algorithm, etc. Realizing SAR image algorithm is worthy of being studied in the domain of EHPC (embedded high performance computing). FPGA is used as a high efficient and low cost solution in EHPC for its high performance and reconfigurable ability. A new phase gradient autofocus (PGA) algorithm for real time case is proposed, which can achieve convergence focusing quality with less iteration and fewer computation loads than the classic PGA algorithm. The principle of how to map the improved algorithm to FPGA architecture is discussed. Some key computing components abstracted from the algorithm, such as CORDIC processor, complex vector correlator and prominent scatter filter are also discussed. The motivation and aim of this work is to develop a numerically efficient, accurate and robust Doppler rate estimator with reasonable architecture in FPGA, which can be used in a high-throughput-rate processor for future onboard imaging system. Because logic resources are effectively used, constraints on volume, weight, and power are easier to meet without sacrifice of losing real-time performance. Experiment result indicates that the improved algorithm reduces iteration times and the precision can satisfy the imaging system.