The Research and Application of a Specific Instruction Processor for AES

Encryption algorithm has been used widely in the embedded trusted computing domain, so how to improve its execution efficiency has become an important issue. The Advanced Encryption Standard (AES) is a new encryption algorithm which has been widely adopted in the field of trust computation due to its high security, low cost and high enforceability. This paper employs a new instruction set architecture (ISA) extension method to optimize this algorithm. Based on the electronic system level (ESL) methodology, a commercial processor tool on the basis of language for instruction-set architectures (LISA) is used to construct an efficient AES application specific instruction processor (AES_ASIP) with the objective to improve the AES algorithm execution efficiency. Finally the AES_ASIP model is implemented in the FPGA (field-programmable gate array) platform. A series of simulations have been conducted to evaluate the performance of the AES_ASIP model. Experimental results show that our processor improves 58.4x% in the execution efficiency and saves 47.4x% in the code storage space compared with the ARM ISA processor.