A Reconfigurable System-on-Chip Design Methodology Based on Function-Level Programming Model

Reconfigurable system on chip (RSoC) is a promising alternative to deliver both flexibility and high computation speed at the same time, and also a technical solution which is looking forward to the future needs of embedded applications market. But its very complex design process is impeding the development of the extensive application. Given the lack of efficiency of the current programming process and resource management, this paper proposes an RSoC design methodology based on function-level programming model on account of the characteristics of the reconfigurable architecture. In the programming model, system designers use high-level language to complete functional specification by calling the co-function-library. Then the dynamic hardware/software partitioning algorithm will decide whether an invoked function should be running on hardware or software automatically. According to the partitioning result, the dynamic linker will switch functions’ execution mode in real time. And the above items facilitate an automatic design flow through specification to the system implementation. Experiments and tests have verified the feasibility and efficiency of the design method.