Transistor-Level Methodology on Power Optimization for CMOS Circuits

With IC technology scaling into nanometer regime, power consumption has become an equal important design constraint as performance. Owing to the shortage of efficient transistor-level delay simulator, previous low-power techniques have to optimize circuits on the gate level. Thanks to the fine granularity, transistor-level low-power design methods can reduce more static power than gate-level counterparts. Thus it is far more important to develop the transistor-level low-power design methodology for nanometer chips marked with high static power. Based on the transistor-level simulator developed, an efficient transistor-level optimization methodology consisting of two-step algorithms is proposed to reduce more static power. The former gate-space algorithm uses the clustering strategy to cut down algorithm complexity. The latter transistor-space algorithm employs fine granularity to pursue reducing more power consumption. Experiments show the following advantages: 1. the proposed methodology is so general that it can analyze and optimize heterogeneous circuit in which each transistor may have its own different V\-\T0\, channel width W, and channel length L, and 2. In the transistor-level W+V\-\T0\+L-sized optimization, the engine takes feasible running time (856.4s for C7552) to cut down 22.85%(average) and 43%(maximum) static power caused by gate-level optimum solution nearly without penalty of active power (average active power increases only 0.02%).