METHODOLOGIES AND STANDARDIZATION OF SOC DESIGN

With the development of VLSI technology, system on a chip （SoC） design is the main solution to handle the increasing design complexity with short time to market. A single chip could reach tens and hundreds millions gates and 500 to 1000MHz operating frequency. To implement such a system, the designers are much more dependent on the reuse of IP blocks. The increasing complexity of SoC, the variation of IP blocks, and many different IP blocks from multiple vendors used in one SoC result in many problems with the reusability of IP blocks. An efficient and feasible method to solve these problems is developing standards for IP block interface, on chip bus and the interface between various EDA tools. The increase of SoC design complexity and embedded software components requires system abstract and hardware/software co design at a higher level, describing the system with popular system design languages, and using more efficient system design methods. In this paper, the IP reuse technology in SoC design is described, the standardization of IP blocks, on chip bus and the interface between EDA tools are introduced, and the system level description languages based on C/C++ extended class library and the platform based SoC design method are discussed.