An Adaptive Dynamic Arbiter for Multi-Processor SoC

As the development of deep submicron technology, the integration of more than one processor on a chip is becoming possible. Multi-processor system-on-a-chip (MPSoC) provides a viable solution to highly parallel computations and communications required by high-end applications. The communication architecture is becoming the bottleneck for MPSoC and a determined element of performance, and efficient arbiter is able to solve the contentions due to simultaneous request accesses in shared bus systems to prevent system performance degradation. A simple adaptive dynamic arbiter that can adjust the bandwidth proportion assigned to every processor automatically to avoid starvation problem in MPSoC environment is presented. The proposed arbiter uses random number generator to select winning processor to solve the problem of fairness in competition. To evaluate the adaptive dynamic arbiter, a gate-level four-core simulation environment is set up and two popular bus arbiters—time division multiplexed arbiter and Lottery bus are implemented. The experimental results show that the proposed one could reduce 68% task execution time, decrease the bus request latency of a processor by 78% and provide better control of the communication bandwidth allocated to individual processor than convention arbiters.