A High-Speed Delay-Independent Synchronous to Asynchronous Interface

This paper proposes a novel interface used in multi-processor system-on-chip and network-on-chip. The interface, which is implemented by the circular FIFO with threshold gate, removes the synchronous clock from sender. It resolves the problems of high power consumption induced by clock signal and low reusability of IP cores. With the transmission mode combining both serial and parallel communication, data of different widths can be transferred from synchronous sender to asynchronous receiver rapidly. Since the distributed framework is utilized, the data transport channel is separated from the transfer control block, as the synchronizer and writeread pointer. In this way, the different reliability of the interface can be satisfied by the interface during changing the number of synchronizer stages. And various asynchronous transport protocols are supported gracefully by the interface. While the two-rail encoding transfer manner is selected, the transmission is quasi-delay insensitive and the data integrity is ensured. Based on SMIC 0.18 μm CMOS technology, simulation results of 3 stages FIFO have shown that the delay is 613ps with the average energy consumption of 3.05pJ for one transfer request responded, which can satisfy the requirements of high speed, low power, strong robustness and good reusability in the design of multiprocessor SoC and network-on-chip.